The central challenge

• AI demand has created an unprecedented surge in demand for computing chips—reportedly 40–50% above existing maximum capacity.
• Meeting that demand requires both more chips and better-performing chips. But production is constrained by the specialized tools and suppliers that fabs depend on, especially ASML’s EUV lithography machines.
• Intel’s executives describe a broader bottleneck: equipment, clean-room capacity, power, water, materials, and the long lead times required to expand manufacturing.

Bringing a new process into production

• A process node takes years to develop. Intel’s 14A process had already been in development for more than three years at the time of the interview.
• Before a node is ready, engineers must finalize its equipment and fine-tune roughly 2,000 manufacturing steps so it can reliably process thousands of wafers each week.
• Yield improves through continual defect detection and troubleshooting:
• Inline metrology identifies defects during manufacturing.
• Electrical testing and wafer sorting reveal failures at the end of the process.
• Engineers cross-section defects and trace them to the relevant manufacturing step.
• Teams test possible fixes, often in parallel.
• Intel uses phase-gate maturity criteria for yield, defects, and performance. Technologies that are not ready are deferred to a later node rather than jeopardizing the schedule.

Lessons from past delays

• Intel’s 10nm process was delayed from its planned 2016 launch to manufacturing in 2018.
• Intel pursued aggressive “hyperscaling” while required tools were unavailable, placing extra burdens on processes and engineers.
• Intel says 10nm eventually achieved strong yield, performance, and cost, but took longer than intended.
• A key lesson was to limit how much innovation is introduced in a single node and prioritize predictable delivery. EUV was one technology Intel judged not ready for 10nm; TSMC adopted it earlier and gained several years of experience.

How transistor technology evolved

• A transistor switches current between a source and a drain, controlled by a gate.
• As transistors shrank, current leakage became harder to prevent, prompting designs that let the gate control more of the channel:
• Planar transistor: gate controls the channel from above.
• FinFET: the channel is a vertical fin; the gate controls it from three sides.
• Gate-all-around (GAA): the channel is divided into thin ribbons, and the gate surrounds each ribbon.
• GAA required new materials and processes, including placeholder layers that are removed after high-temperature steps, followed by a high-k insulator and metal gate.
• Ideas can take decades to reach mass production. Engineers must solve material, equipment, integration, and reliability problems—and decide when the performance benefits justify adopting the technology.

Lithography, High-NA EUV, and backside power

• Intel is using High-NA EUV as an option for 14A. Its higher numerical aperture can print smaller features in a single exposure, potentially reducing multiple patterning steps and defect risk.
• High-NA tools cost substantially more, so their value depends on whether they save enough manufacturing time and improve yields.
• Intel’s backside power design moves power wiring beneath the transistors, freeing space for signal wiring above them.
• Intel says this architecture can make High-NA more useful: it can print certain patterns in one pass, while a design without backside power may still need multiple passes.
• High-NA is an option in Intel’s 14A design kit, with adoption discussed customer by customer.

Foundry operations and customer design kits

• Intel historically manufactured mainly for its own products and did not use the same formal customer-facing process design kit (PDK) model as a dedicated foundry.
• Becoming a foundry has required Intel to learn what external customers expect from PDK quality, maturity, and documentation.
• Intel says 14A is intended to have a high-quality PDK from the start, with maturity measured in stages and improved through customer feedback.

Research beyond current production

New materials and transistor architectures

• Intel is researching ruthenium for extremely narrow wires. Unlike copper, it may not need a liner, which can make it more competitive at very small dimensions.
• Material choices can change as tools and processes improve: Intel describes cobalt as once having the advantage, with copper later becoming more competitive.
• CFETs stack n-type and p-type transistors vertically to save area. Challenges include making deep, narrow connections and filling them without voids.
• Researchers use simplified “short-loop” test structures—such as diodes, capacitors, and basic transistors—to test components faster than a full manufacturing flow.
• 2D materials can be deposited at atomic-scale thickness, but may fail if they do not adhere, remain stable, or withstand later processing.

Heat and 3D scaling

• More vertical stacking could enable much denser chips, but heat dissipation becomes a major constraint.
• Compute is limited by switching speed, power efficiency, and the ability to remove heat. Intel says tools for system-level thermal analysis are still developing, but treats heat as a solvable engineering challenge.

Managing experiments and factory priorities

• Intel’s “Hot Topics” meetings prioritize urgent problems and allocate engineering resources.
• The company says engineers often must decide with incomplete data; waiting for certainty can mean losing the opportunity to act.
• A defect example involved abnormal growth during epitaxy, the process used to grow source and drain material. These “nodules” can cause shorts between transistors.
• The factory can assign experiments different priority levels through “hot boxes.” The highest-priority lots move rapidly through tools, but this disrupts factory efficiency, so the resource is used selectively.

Advanced packaging: connecting chips

• As computation grows, moving data between chips can become as important as computation itself. Chip area—and thus compute—can grow faster than the edge length available for connections.
• Packaging has progressed from side-by-side chips to silicon interposers and then to direct chip bonding.
• Hybrid bonding joins copper connections directly, without bulky solder bumps, enabling much denser and shorter connections.
• Intel distinguishes:
• Wafer-to-wafer bonding: bonds whole wafers, but requires matching dies and yield patterns.
• Chip-to-wafer bonding: selects tested, known-good dies and places them on a base wafer, making it practical for mismatched designs.
• Hybrid bonding can improve bandwidth and reduce energy per bit, potentially lowering power and heat for both AI systems and other devices.
• The technology has a long scaling runway: Intel described production pitches of 25 micrometers, sub-10-micrometer development, and research results at much finer pitches.

Capacity, economics, and the AI boom

• ASML produces fewer than 100 EUV machines per year, and the supply must serve Intel, TSMC, memory makers, and others.
• Tool availability is not the only constraint: once a process is qualified, fabs often need a specific tool and cannot simply substitute another supplier’s equipment.
• Intel aims to reuse as much equipment as possible between nodes, while adding specialized tools for new capabilities.
• Intel estimated that, with existing global constraints, leading-edge wafer output might grow roughly twofold, but not tenfold.
• Foundry economics depend heavily on scale: fabs have enormous fixed costs, so higher utilization and improved yields can produce disproportionately more output from the same facility.
• Intel’s CTO said catching up with TSMC involves more than comparing transistor density. Performance, power, area, yield, timing, and multiple transistor and memory types all matter. Reliable, high-yield production is especially important.
• The discussion suggests that demand may outpace supply for years: new tools can take around 18 months to arrive, while building new fab capacity can push expansion toward the end of the decade.
• Intel is open to working with Elon Musk’s proposed Terafab, but new fabs also require tools, clean rooms, power, water, and other resources.
• Intel’s CTO said that, in hindsight, the company would have invested more in tools a year earlier and expects to invest more going forward.

Overall takeaway

AI is putting unprecedented pressure on semiconductor production, but expanding supply is not as simple as spending money. It requires coordinated investment across equipment suppliers, fabs, materials, packaging, and infrastructure. At the same time, process development depends on balancing innovation against yield, cost, and schedule—and on making decisions before all the data is available.